B-TSP: An Advanced Power Safe Management Strategy for modern Multi-core Platforms under Thermal-Aware Design
Ref: CISTER-TR-230612 Publication Date: 8, Jun, 2023
B-TSP: An Advanced Power Safe Management Strategy for modern Multi-core Platforms under Thermal-Aware Design
Ref: CISTER-TR-230612 Publication Date: 8, Jun, 2023Abstract:
Thermal management is a crucial aspect of the design and operation of safety-critical multi-core architectures, as their high power density can cause significant heat generation and risk of thermal overload. If not properly managed, thermal overload can lead to system failures and performance degradation, which is a major challenge for system designers. To address this challenge, advanced core mapping solutions have become increasingly popular in both industry and academia. In this paper, we present key insights, techniques and results on thermal management in multi-core architectures. We propose a new per-core power budget strategy called that is scalable and enables system performance optimization while abstracting from mapping concerns. In addition, we present a new strategy called that allows us to derive worst-case mappings as a function of the number of active cores from a power consumption perspective in a thermal-aware design. We demonstrate the effectiveness of our solution through intensive simulations with the homogeneous AMD EPYC 7351 16-cores platform.
Javier Pérez Rodríguez
Yilian Ribot
Patrick Meumeu Yomsi
Luis Puente LamDocument:
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DownloadProceedings of the 31st International Conference on Real-Time Networks and Systems (RTNS 2023).
Dortmund, Germany.
Record Date: 7, Jun, 2023