Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling
Ref: CISTER-TR-210206 Publication Date: 7 to 9, Apr, 2021
Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned SchedulingRef: CISTER-TR-210206 Publication Date: 7 to 9, Apr, 2021
Multicore platforms are being increasingly adopted in Cyber-Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared system bus that connects the cores to the memory hierarchy (including caches and main memory). However, such hierarchy causes tasks running on different cores to compete for access to the shared system bus whenever data reads or writes need to be made. Such competition is problematic as it may cause large variations in the execution time of tasks in a non-deterministic way. This paper presents an approach that allows one to derive the worst-case response-time of tasks that follow the 3-phase task model executing under partitioned scheduling. Experiments on synthetic task sets were performed to evaluate the effectiveness of the proposed analysis in comparison to state-of-the-art. The experimental results reveal an increase of up to 34 percentage points of schedulable task sets in comparison to the state-of-the-art.
29th International Conference on Real-Time Networks and Systems (RTNS 2021), Technical Session.